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ZYXOW is set whenever a new acceleration data is produced before completing the retrieval of the previous set. This event
occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been overwritten. ZYXOW
is cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the active channels are
read.
ZOW is set whenever a new acceleration sample related to the Z-axis is generated before the retrieval of the previous sample.
When this occurs the previous sample is overwritten. ZOW is cleared anytime OUT_Z_MSB register is read.
YOW is set whenever a new acceleration sample related to the Y-axis is generated before the retrieval of the previous sample.
When this occurs the previous sample is overwritten. YOW is cleared anytime OUT_Y_MSB register is read.
XOW is set whenever a new acceleration sample related to the X-axis is generated before the retrieval of the previous sample.
When this occurs the previous sample is overwritten. XOW is cleared anytime OUT_X_MSB register is read.
ZYXDR signals that a new sample for any of the enabled channels is available. ZYXDR is cleared when the high-bytes of the
acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the enabled channels are read.
ZDR is set whenever a new acceleration sample related to the Z-axis is generated. ZDR is cleared anytime OUT_Z_MSB register
is read.
YDR is set whenever a new acceleration sample related to the Y-axis is generated. YDR is cleared anytime OUT_Y_MSB register
is read.
XDR is set whenever a new acceleration sample related to the X-axis is generated. XDR is cleared anytime OUT_X_MSB register
is read.
Data Registers: 0x01: OUT_X_MSB, 0x02: OUT_X_LSB, 0x03: OUT_Y_MSB, 0x04: OUT_Y_LSB, 0x05: OUT_Z_MSB,
0x06: OUT_Z_LSB
These registers contain the X-axis, Y-axis, and Z-axis 12-bit output sample data expressed as 2's complement numbers. The
sample data output registers store the current sample data.
0x01: OUT_X_MSB: X_MSB Register (Read Only)
Bit 7
XD11
Bit 6
XD10
Bit 5
XD9
Bit 4
XD8
Bit 3
XD7
Bit 2
XD6
Bit 1
XD5
Bit 0
XD4
0x02: OUT_X_LSB: X_LSB Register (Read Only)
Bit 7
XD3
Bit 6
XD2
Bit 5
XD1
Bit 4
XD0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0x03: OUT_Y_MSB: Y_MSB Register (Read Only)
Bit 7
YD11
Bit 6
YD10
Bit 5
YD9
Bit 4
YD8
Bit 3
YD7
Bit 2
YD6
Bit 1
YD5
Bit 0
YD4
0x04: OUT_Y_LSB: Y_LSB Register (Read Only)
Bit 7
YD3
Bit 6
YD2
Bit 5
XD1
Bit 4
XD0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0x05: OUT_Z_MSB: Z_MSB Register (Read Only)
Bit 7
ZD11
Bit 6
ZD10
Bit 5
ZD9
Bit 4
ZD8
Bit 3
ZD7
Bit 2
ZD6
Bit 1
ZD5
Bit 0
ZD4
0x06: OUT_Z_LSB: Z_LSB Register (Read Only)
Bit 7
ZD3
Bit 6
ZD2
Bit 5
ZD1
Bit 4
ZD0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the auto-
incrementing address range of 0x01 to 0x06 to reduce reading the status followed by 12-bit axis data to 7 bytes. If the F_READ
bit is set (0x2A bit 1), auto-increment will skip over LSB registers. This will shorten the data acquisition from
7 bytes to 4 bytes. The LSB registers can only be read immediately following the read access of the corresponding MSB register.
A random read access to the LSB registers is not possible. Reading the MSB register and then the LSB register in sequence
ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the
MSB and the LSB byte.
0x0B: SYSMOD System Mode Register
The system mode register indicates the current device operating mode. Applications using the Auto-SLEEP/WAKE mechanism
should use this register to synchronize the application with the device operating mode transitions.
0x0B: SYSMOD: System Mode Register (Read Only)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
SYSMOD1
Bit 0
SYSMOD0
MMA8452Q
Sensors
20
Freescale Semiconductor, Inc.
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